C952 Computer Architecture - Set 2 - Part 3

Test your knowledge of technical writing concepts with these practice questions. Each question includes detailed explanations to help you understand the correct answers.

Question 41: What is the "miss penalty" in memory hierarchies?

Time to transfer cache data to CPU

Delay caused by cache coherence errors

Time needed to fetch data into cache from main memory

Execution time for high-priority processes

Question 42: What is "NOP" in assembly language?

Negative operating procedure

Next operational process

No operation instruction

Non-operational program

Question 43: Which I/O scheme notifies the CPU when a device needs attention?

Direct memory access

Polling

Interrupt-driven I/O

Cycle stealing

Question 44: Which cache design allows instructions and data to be stored separately for faster access?

Write-through cache

Set-associative cache

Split cache

Fully associative cache

Question 45: What term describes combining data into logically sequential blocks to speed up access times?

Multithreading

Prefetching

Striping

Threading

Question 46: Which synchronization device allows only one processor access to data at a time?

Barrier

Lock

Semaphore

Latch

Question 47: Which memory system is organized in levels with faster, smaller memories near the CPU?

Memory hierarchy

RAID

LRU cache

Cache coherence

Question 48: What purpose does a "hot-swapping" capability serve in a system?

Allows processors to communicate directly

Enables hardware replacement while the system is running

Synchronizes memory data

Transfers data without latency

Question 49: Which type of bandwidth measures the worst-case split of network data across multiprocessor nodes?

Bisection bandwidth

Transfer bandwidth

Throughput bandwidth

Network bandwidth

Question 50: Which memory technique keeps frequently used address mappings in a special cache?

Error detection code

Page mapping

Translation Lookaside Buffer (TLB)

Address translation

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